Kyrillos Magdi GHOBRIAL
Grenoble
Summary
Junior Hardware ASIC Digital Design Verification Engineer with a strong passion for communication technologies and complex system verification. Experienced in ASIC verification across the engineering development cycle, with hands-on expertise in UVM-based testbenches, components, and VIP development for industry-standard communication protocols, including AMBA (AXI, AHB, APB), I2C, and SMBus. Recognised for my commitment, precision, and problem-solving skills, I am eager to contribute to an innovative and challenging environment, working on cutting-edge, large-scale verification projects.
Overview
2
2
years of professional experience
Work History
Hardware ASIC Design Verification Engineer
AEDVICES
08.2023 - Current
- I2C/SMBUS VIP Development: Worked on I2C Burst layer, 10-bit addressing, and NACK handling (stop-start/restart configurable feature)
- Developed I2C test sequences (for Normal/Burst modes, and Single/Multi-Master) and UVM callbacks
- Implemented several SMBUS VIP test cases
- AMBA VIPs Enhancement & Verification: Delivered VIP status reports (for APB, AHB, AXI-Stream, AXI) covering feature matrices, tool/UVM version support, coverage gaps, and standard-version configurability
- Implemented AXI functional coverage (transactional + SVA-based handshake checks) and test sequences for OOO, interleaving, locked accesses, QoS, and region-based security
Confidential Client
02.2024 - Current
- Project: Subsystem Verification of RISC-V Debugger Integration: Conducted SV class-based subsystem verification for integrating a JTAG-based debugger compliant with RISC-V External Debug Support with a 32-bit RISC-V CPU
- Developed verification plan with detailed test case scenarios descriptions, coverage goals, and environment development time estimation
- Designed the verification environment architecture and developed UML diagrams to document the structure
- Implemented a generic JTAG VIP supporting configurable IR length, location in chain, TAP bypass, and designed an SV dummy JTAG TAP model for use in generic test cases
- Implemented a RISC-V Debugger-specific VIP, extending the JTAG VIP with specialized test cases: Core control (halt/run, single-stepping, triggers)
- Core registers/memory access (using abstract commands, system bus, program buffer)
- Error case testing of unsupported features
- Technical documentation for environment architecture, VIP usage, testcase library
- Project: Subsystem verification of an EEPROM Memory Shell (Ongoing): SV class-based IP block level verification of the digital HDL model of an EEPROM memory, implementing test cases for all the memory IP features
- Verification plan with detailed test case descriptions and environment development time estimation for the digital memory shell interfacing the memory IP with Wishbone bus protocol
- Verification environment architecture for memory shell
- SV class-based subsystem level verification of memory digital shell, implementing test cases according to the developed verification plan
Education
Bachelor of Science - Electronics & Electrical Communication Engineering
Ain Shams University
06.2022
Skills
- HDVLs & Verification Methodologies
- SystemVerilog
- UVM
- Verilog
- VHDL (Basics)
- Protocols
- I2C
- SMBUS
- SPI
- APB
- AHB
- AXI-Stream
- AXI
- C/C
- MATLAB/SIMULINK
- TCL
- Pythons
- Linux OS & File System Management
- Synopsys Design Compiler
- Synopsys Spyglass
- Synopsys VCS
- Synopsys TetraMax
- Xcelium
- Questasim/Modelsim
- Xilinx Vivado
- Intel Quartus Prime
- TCL Shell
- SIGASI
Credly
https://www.credly.com/users/kyrillos-magdi.70134743
Personal Information
Nationality: Egyptian
Courses And Trainings
- Digital Verification Analyst Diploma, Under supervision of Eng.Sherif Hosny, 11/01/22, 01/31/23
- Digital IC Design Track Six-Month Training at Si-Vision Academy, 11/01/22, 05/31/23
- Digital IC Design Diploma, Under supervision of Eng. Ali El-Temsah, 07/01/21, 09/30/21
- Digital PnR Physical Design Course, Under supervision of Eng.Islam Samir, 03/01/23, 05/31/23
Timeline
Confidential Client
02.2024 - Current
Hardware ASIC Design Verification Engineer
AEDVICES
08.2023 - Current
Bachelor of Science - Electronics & Electrical Communication Engineering
Ain Shams University
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