Summary
Overview
Work History
Education
Skills
Languages
Timeline
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Ehtesham Ali Khan

Valence

Summary

FPGA Developer | International Master's in Embedded Systems Security | Grenoble INP - Esisar, UGA

FPGA Design Engineer with over 7 years of experience in VHDL/Verilog RTL design, signal processing, and embedded systems. Proficient in the full development lifecycle, from RTL design and timing closure (STA, CDC) to CI/CD automation and hardware validation. Skilled with Intel, AMD, Lattice, and Microchip FPGAs. Currently, I am developing FFT acceleration on RISC-V for my master's innovation project. Basic French.

Seeking an internship in FPGA/RTL design, electronics, digital signal processing, SoC architecture, or embedded systems development.

Overview

7
7
years of professional experience

Work History

FPGA Developer

Ericsson Hungary
BUDAPEST
08.2023 - 06.2025
  • Developed VHDL-based TDM synchronization for 5G core network on Altera FPGAs
  • Automated CI/CD pipeline (Jenkins, Git, Gerrit) and authored technical documentation
  • Performed timing closure (STA, CDC) and hardware validation using oscilloscopes, spectrum analyzers, logic analyzers, and Calnex Paragon-x
  • Managed projects using Jira and maintained design specification documents

Embedded and FPGA Developer

Advanced Telecom Solutions Pvt. Ltd. (ATSL)
Haripur
01.2018 - 04.2023
  • Developed RTL (VHDL/Verilog) for signal processing, implementing filters, channelization, and AM/SSB waveforms on Zynq SoC and FPGAs.
  • Designed high-speed ADC/DAC interfaces (SPI, AXI, Ethernet) and optimized throughput/latency for DSP systems.
  • Implemented security solutions including AES-256 and key management on custom crypto hardware.
  • Conducted full system validation: testing receiver/transmitter performance (sensitivity, THD) and debugging with lab equipment (oscilloscopes, spectrum analyzers).
  • Performed Static Timing Analysis (STA), resolved CDC issues, and managed timing closure for DDR3/4 interfaces.
  • Performed system-level hardware validation using lab equipment (oscilloscopes, spectrum/signal/network analyzers)

Education

International Master in Embedded Systems Security

Grenoble INP - Esisar, UGA
Valence
09-2026

Bachelor of Science - Electrical Computer

University of Engineering And Technology
Taxila
07-2017

Skills

  • VHDL/Verilog development
  • FPGA design
  • Hardware validation
  • Automation tools
  • Project management
  • Technical documentation
  • Team collaboration
  • Signal processing
  • Security solutions
  • Hardware development
  • C proficiency
  • Embedded system
  • Embedded C programming
  • Regression testing
  • C# programming
  • Electronics lab testing and analysis
  • Critical thinking proficiency
  • Pcb debugging
  • Logic Analyzer

Languages

English
Proficient (C2)
C2
French
Beginner
A1

Timeline

FPGA Developer

Ericsson Hungary
08.2023 - 06.2025

Embedded and FPGA Developer

Advanced Telecom Solutions Pvt. Ltd. (ATSL)
01.2018 - 04.2023

International Master in Embedded Systems Security

Grenoble INP - Esisar, UGA

Bachelor of Science - Electrical Computer

University of Engineering And Technology
Ehtesham Ali Khan