ABDUL RAUF
Barcelona
Summary
Dedicated and skilled Verification Engineer with 4 of experience in verifying complex digital designs and ensuring their functionality. Proficient in various verification methodologies, tools, and languages.
Overview
4
4
years of professional experience
Work History
Design Verification Engineer
Barcelona Supercomputing Center
02.2023 - Current
- "Verification of Multicore SoC (PERTE) project. This project is based on Intel's Horse Creek SoC and BSC RISCV cores."
- Developed subsystem-level verification environment for the design block implemented on the OpenPiton Platform.
- Integrated third-party VIPs (AXI, JTAG, UART) and different verification models to ensure verification of different IP blocks present in the Subsystem design block.
- Verification of the JTAG protocol and its access to the Subsystem Internal design block via Debug Ring.
- Integrated AXI-Behavioral UART module to add support implementation of the Linux-Bootrom and OpenSBI platform.
- Verification of NOC to AXI4-DMA bridge.
"Verification of the MEEP (MareNostrum Experimental Exascale Platform) project."
- Developing UVM infrastructure to verify designs at the subsystem level with multiple design blocks.
- Integrated third-party VIPs along with other verification models and environments verifying different sub-blocks inside Subsystem RTL (based on OpenPiton Platform www.openpiton.org).
Design Verification Engineer
Rapid Silicon
12.2021 - 01.2023
- Worked on the Verification of an IO - Bank (includes SERDES-based architectural unit) inside the physical layer of a high-speed protocol (MIPI - DPHY)
- Developed and Implemented UVM-based Verification Environment for the Verification of IO-Bank aimed to achieve 100% functional coverage for the IO-Bank
- Worked in a team of six-member for the verification and coverage completion of an SoC based on a RISC-V processor (U74-MC)
- Implemented Performance Monitor and detected higher latency points between different sub-systems.
Associate Design Verification Engineer
Lampro Mellon
01.2020 - 12.2021
- Onboarding & Verification of Synopsys GPIO IP, UART-IP and Timer IP on a RISC-V-based SoC
- UVM-based verification environment to verify Peripherals i.e GPIO on SoC Level, Implemented Mailbox methodology as synchronizer between C-test environment and UVM Environment
Education
Bachelors in Electrical Engineering -
FAST - National University of Computer And Emerging Sciences (NUCES)
Lahore, Pakistan06.2018
Skills
- Verilog/SystemVerilog
- C/C
- UVM
- ModelSim/VCS/QuestaSim
- Python/Shell Scripting/Makefile
- Git/SVN
- Scripting languages proficiency
Timeline
Design Verification Engineer
Barcelona Supercomputing Center
02.2023 - Current
Design Verification Engineer
Rapid Silicon
12.2021 - 01.2023
Associate Design Verification Engineer
Lampro Mellon
01.2020 - 12.2021
Bachelors in Electrical Engineering -
FAST - National University of Computer And Emerging Sciences (NUCES)
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